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[VHDL-FPGA-Verilog] ethernet_test

Description: Verilog implementation of ethernet mac 100mbps test
Platform: | Size: 3072 | Author: Emre LEVENT | Hits:

[VHDL-FPGA-Verilog] eth

Description: 用数字逻辑语言描述以太网，百兆以太网MAC和MII的verilog源码-With digital logic language to describe Ethernet
Platform: | Size: 123904 | Author: 胡封 | Hits:

[source in ebook] ethenete

Description: 基于verilog的三速以太网源程序，文件中包含源程序和测试程序。-tri_model ethernet source code based on vhdl languange, include source code and testbench in the file.
Platform: | Size: 123904 | Author: chenzhi | Hits:

[OS program] Chapter10-Sample

Description: 此代码是用Verilog实现的以太网接口-This code is an Ethernet interface implemented using Verilog
Platform: | Size: 123904 | Author: `ians | Hits:

[VHDL-FPGA-Verilog] FPGADM9000AVerilog

Description: FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
Platform: | Size: 4200448 | Author: `ians | Hits:

[VHDL-FPGA-Verilog] FPGADM9000AVerilog

Description: FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
Platform: | Size: 2800640 | Author: 飞翔 | Hits:

[Other Embeded program] CycloneIII_ethernet

Description: CycloneIII + receive/transmit ethernet packets. Verilog
Platform: | Size: 2328576 | Author: Th | Hits:

[Software Engineering] verilog_mac

Description: 该文档详细描述了以太网mac层的功能与实现，里面包括了verilog程序-The document describes in detail and implementation of Ethernet MAC layer functions, which includes the Verilog program
Platform: | Size: 704512 | Author: MR_shang | Hits:

[VHDL-FPGA-Verilog] PHY_MDIO

Description: 光纤模块实现点对点通信，千兆网传输，基于FPGA，采用Verilog语言进行编程，实现千兆网模块的高速传输-Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module
Platform: | Size: 1111040 | Author: Grace | Hits:

[VHDL-FPGA-Verilog] K7_1M

Description: 用Verilog语言实现的以太网驱程，可最多实现8个以太网，外加PHY后，可实现ping操作-Ethernet drive-by Verilog language can achieve up to eight Ethernet, plus after PHY, can achieve a ping
Platform: | Size: 6008832 | Author: 罗军 | Hits:

[Other] verilog-ethernet-master

Description: sivasankar is a good boy,,, njknsdjnjkgnjskn sjnkdnsgkjndjks jdskgnskdndgksj ksnklgnkl
Platform: | Size: 943104 | Author: sankula sivasankar | Hits:

[VHDL-FPGA-Verilog] ethmac10g_latest.tar

Description: ethmac10g_latest是用verilog编写的10gbps的以太网mac，对工程开发非常有用！-ethmac10g_latest is written in verilog 10gbps Ethernet mac, very useful for the development of the project!
Platform: | Size: 789504 | Author: hezigang | Hits:

[VHDL-FPGA-Verilog] ethmac10g_latest.tar

Description: 10G高速以太网mac VERILOG源码 可仿真可实现-10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation
Platform: | Size: 789504 | Author: 王凯 | Hits:

[VHDL-FPGA-Verilog] eth

Description: 基于verilog语言的以太网接口的fpga实现，用在无线通信领域，供参考-The Ethernet interface based on verilog language fpga implementation, used in the field of wireless communications, for your reference
Platform: | Size: 24576 | Author: 小刚 | Hits:

[Other] xge_mac_latest.tar

Description: 用Verilog编写的以太网控制器，可以使用，里面是全部verilog源码-Ethernet controller based on Verilog, can be used directly, all verilog files
Platform: | Size: 1128448 | Author: 王二小 | Hits:

[VHDL-FPGA-Verilog] ethernet_test

Description: 以太网FPGA通信,verilog代码，实现双向通信-Ethernet FPGA communication
Platform: | Size: 2186240 | Author: 徐辉 | Hits:

[VHDL-FPGA-Verilog] udp_send1

Description: 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data
Platform: | Size: 53248 | Author: qiubin | Hits:

[TCP/IP stack] UDP

Description: 利用verilog语言写的基于千兆网卡的UDP协议驱动-Use verilog language written based Gigabit Ethernet UDP protocol driver
Platform: | Size: 4682752 | Author: 孟凡良 | Hits:

[VHDL-FPGA-Verilog] 14_ethernet_test

Description: 这是利用FPGA实现对以太网传输的控制。FPGA为Spartan 6 LX16，以太网芯片为RTL8211。千兆传输速率。语言为Verilog，但没找到这一选项，故选择了最接近的VHDL-This is achieved using the FPGA Ethernet transmission control. FPGA for the Spartan 6 LX16, Ethernet chip RTL8211. Gigabit transmission rate.
Platform: | Size: 7380992 | Author: accountm | Hits:

[Internet-Network] ETH_GEN_CHK

Description: Ethernet packet generator and check (verilog),for Ethernet design purpose!
Platform: | Size: 3072 | Author: min | Hits:
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